1. Field of the Invention
This invention is related to power management in a microprocessor. More specifically, this invention has to do with mechanisms for managing the clocking within a microprocessor, so that clocks in the microprocessor can be altered over time. In the type of clocking system involved, a clock source drives clock generator logic which derives multiple clock signals and feeds the signals to registers in various hardware units within the microprocessor. Clock management allows the power consumption of the microprocessor to be reduced when normal clocking of some units within the microprocessor is not needed.
2. Description of the Problem
Many microprocessor-based systems are designed to minimize the amount of power consumed by the system. This power minimization is especially important for battery operated systems. Techniques are needed both in the design of the system itself and in the design of the integrated circuits used in the system. For example, a microprocessor or embedded controller in the system may need to use sophisticated mechanisms for controlling the power consumed by the microprocessor. These mechanisms often employ control registers that are manipulated by software which is running in the system. Writing a particular value to such a register may cause the power management logic to alter the clocking signals to some hardware units within the processor, shutting off clock signals to some or even all circuitry within some units to reduce power consumed during operations where not all units in the processor are needed. In some cases, the frequency of specific clocking signals may be reduced as opposed to having the clock signal shut off.
Clock disabling mechanisms used to disable clock signals in a microprocessor fit roughly into six categories. The mechanisms in some categories have a more severe effect on the operation of the microprocessor than the mechanisms in others. If the clock disabling is more severe, the clock signal is disabled closer to its source and farther from a register where the signal is used to latch information. To use a water supply analogy, the most severe mechanism would be to stop the flow of water from a dam into the water company. A less severe would be to turn off the tap at an individual faucet in a home. The six categories of clock disabling power management can be described from least severe to most severe as follows:
1. Supply normal clock signals. PA1 2. Reduce clocking frequency but continue to supply clock signals. PA1 3. Disable clock signal at each register where it is used, with the clock signal itself being switched and delivered to each hardware unit register. PA1 4. Gate off clock signal after the clocks are generated, but before being delivered to each register. PA1 5. Disable clock generator but leave clock source active. PA1 6. Disable clock source.
The more severe modes of clock disabled power management result in greater reduction in power consumption, but have a greater impact on overall performance because they require more time to exit and resume normal clocking.
The entering into and waking up from clock disabling power management modes in currently handled by a mixture of software and hardware control. Software controls the entry into a clock disabling mode and hardware controls the waking up from a clock disabling mode. Software first ensures that a microprocessor hardware unit that is to have the clocks altered is idle. Shutting off clocks effectively powers down the unit in question; therefore, clock disabling modes are called powered-down modes. The unit must be ready to be powered-down. That is, the unit must not be in the middle of performing some operation. Once the software has confirmed the unit is ready to be powered-down, the software manipulates a clocking control register to affect the clock signals sent to the appropriate hardware unit. When it is time to wake up the hardware unit, an event in the system causes an interrupt, which automatically disables the powered-down mode and restores the clocks to normal clocking. The affected unit then resumes normal operation.
The problem with the above approach is that the software management of the entry of a powered-down mode requires specialized, hardware-specific software and it may take many cycles to complete the required actions. Therefore, powered-down modes will only be used under drastic circumstances where a microprocessor unit will be in a powered-down mode for a relatively long period of time. However, it is common for there to be frequent, short periods when a microprocessor hardware unit is either not needed, or could have its performance reduced by lowering the frequency of one or more of its clocks. What is needed is a hardware based mechanism that allows a microprocessor to handle power management in an efficient, dynamic fashion, so that power can be saved at all opportunities, without requiring software intervention.